Voltage Loop Design
Project Ultimate™ @ SMPS Power Supplies


This is the simplified voltage loop schematic used to simulate with PSpice the Bode plots.
The goal for this design approach is to have the Loop Gain intersect the zero db at the frequency set as the goal in Excel file.
Also, have a 20dB Gain slope when intersecting the zero db.
To achieve the 20dB Gain slope, the decision was made to compensate any pole in the power train with a zero at the same frequency in the voltage compensation loop, and any zero in the power train with a pole at the same frequency.


Above are the PSpice simulated Bode plots, showing a perfect corelation with the Voltage Loop design goals, and demonstrating the Excel file proper calculations for the Voltage Loop compensation components.


The simplified Excel file used to calculate the poles and zeros of the voltage compensation loop.
The assumption is that the proper topology for the application is already chosen, and the voltage regulation loop is using an inner current mode controller, with known gain.