SMPS Power Supplies

Site Directory:

PSpice Simulation
Excel Design files
SMPS Design Help
Get free software

Prometheus Project
Nemesis Project

Discussion Forum
Voltage Loop Design
Solid State Lighting
Design Resources
SMPS terminology


Power Supply Manufacturers db

Power Electronics
News & Forum

Power Lab

LLC Average Model
MOSFET switching
Flyback Design
Current Doubler
GaN or Silicon?
Boost PFC math
EN 50082-1

SMPS on LinkedIn

Privacy Policy

Current Doubler Topology - Myth and Reality by Constantin Darius Livescu

To our knowledge, this is the first article (and the only one to date), to realistically compare the Center Tap power supply topology with the Current Doubler equivalent using waveforms and numbers, and not "feelings" or "qualitative" explanation of what is happening. In this article, the reader will find actual calculations and simulation waveforms of main parameters.

It is unfortunate that far too many technical articles are concentrating on an extremely narrow aspect of a particular problem, ignoring that the problem is part of a much wider picture. It is true that, in order to analyze a phenomenon, an engineer, a scientist, or a doctor must break a problem in smaller pieces, being easier to handle and analyze. But ignoring the bigger picture is misleading the reader.

There are several articles out there regarding the "Current Doubler" topology and describing the advantages of using it. Unfortunately, none of them (or at least none of those published in reputable magazines, proceedings, or written by well-known designers) are telling the whole story. This article is an attempt to give readers a much more accurate image of what actually happens when you decide to use a "Current Doubler" topology instead of a "Center Tap".

We will consider, for our analysis, the DC/DC section of the following switch mode power supply:
  • Vin=407Vdc
  • Vout=27.22Vdc
  • Iout=90A
  • (Pout=2.5kW)
  • fsw=200kHz (we will use as a definition of the switching frequency, the frequency "seen" by the power/isolation transformer)
  • Duty Cycle=0.793
Three options will be considered:
  • "Center Tap"
  • "Current Doubler", with the output inductors value chosen to preserve the same primary currents as "Center Tap"
  • "Current Doubler 2", with the output inductors value chosen twice the value used in the "Center Tap"

Following is a table summarizing the results for the three power supply topologies. You can see also the corresponding waveforms or calculated values, by clicking on the highlighted parameter.

Parameter\Topology Center Tap Current Doubler Current Doubler 2
Lout 1 x 0.70 uH 2 x 7.68 uH 2 x 1.40 uH
Cout 5 x 1,800 uF 1 x 1,800 uF 5 x 1,800 uF
Vout ripple p-p 80 mV 75 mV 80 mV
E Lout 0.0028 J 0.0156 J 0.0184 J
E Cout 3.334 J 0.667 J 3.334 J
E total 3.337 J 0.683 J 4.020 J
Ipk primary 10.0 A 10.0 A 14.6 A
Irms primary 8.3 A 8.3 A 9.0 A
Pcu secondary 11.9 W 7.7 W 8.8 W
Ptr total 17.3 W 13.1 W 14.8 W
Irp p-p Lout 25 % 25 % 137 %
Ipk Lout 101.3 A 50.6 A 75.8 A
Ip-p Lout 22.5 A 11.3 A 61.7 A
Iac Lout 6.5 A 3.2 A 17.8 A
Pcu Lout 1.3 W 2 x 5.5 W 2 x 2.3 W
Pcore Lout 0.7 W 2 x 0.2 W 2 x 2.9 W
Ptotal Lout 2.0 W 2 x 5.7 W 2 x 5.3 W
Ptotal magnetics 19.3 W 24.5 W 25.4 W

And now the comments regarding this power supply topology:

Myth: " ... operation on the primary side, including duty-cycle is unchanged ... diode and output capacitor stresses are identical to full-wave technique ... "

  • Identical operation on the primary side and identical stress on IDENTICAL output capacitors can not be achieved simultaneously. From the table and waveforms shown above it becomes clear that you have two major options (among many other), that you can choose from.
  • One major option would be to preserve, relative to the "Center Tap", the same operation in the primary side (peak and RMS primary current). By doing that, you need the output inductors to have, each of them, an inductance 11 times higher than the "Center Tap" design! You have a benefit by doing this, the output capacitor can have 5 time lower capacitance than the "Center Tap", for the same OUTPUT VOLTAGE RIPPLE.
  • Second option would be to preserve the SAME OUTPUT VOLTAGE RIPPLE, using the SAME OUTPUT CAPACITANCE as the "Center Tap". This would allow you to use a value for the output inductors twice the value used in the Center Tap topology, value that is suggested in most articles describing the Current Doubler topology. However, this approach will change drastically the current shape in the primary of the power transformer. In our example, the peak current changed by almost 50%. Someone may argue that this is not that bad. This is absolutely true, and actually may be beneficial in achieving soft switching. However, this kind of reasoning logically is fundamentally flawed, as one would not compare apple with apple. If you decide that a higher peak current in the primary side is acceptable (or desirable), you should go back, and analyze also a center tap topology with a higher ripple current. Therefore, we consider a MUST to compare Center Tap topology with the equivalent Current Doubler having the SAME primary currents. Otherwise we would compare apple with pears and not apple with apple.

Myth: " ... the current doubler working under same conditions as a full wave rectifier will reduce the copper loss in the transformer secondary by approximately 50% ... "

  • First, the 50% claim is for secondary copper loss, not for total transformer loss. In our example, if you maintained the same currents in the primary, the secondary copper loss decreased by approximately 35%. If you considered using the output inductors twice the value of the center tap configuration, the secondary loss decreased only by 26%, while the primary loss INCREASED by 14%! This is because, not preserving same input current waveshape, the rms value of the primary and secondary will increase.
  • Second, the TOTAL MAGNETICS LOSSES may increase when you change the output stage topology from center tap to current doubler! In our example, the total magnetics losses increased by 27%, or 31.6% if you have not used the correct current doubler equivalent circuit.
  • In our personal opinion, the secondary copper loss can realistically be reduced by approximately 35%, if you are using an "optimum design", using methodologies like the ones described in papers written by Dowell, Jongsma, Carsten, etc. This reduced secondary copper loss would result in a typical reduction of the total power transformer loss of 25%. This could mean A LOT, or NOTHING for a power supply efficiency, depending on the application!!!
Other Power Supply design considerations:
  • First of all, we compared the two topologies using an example, because it was easier to see the advantages and disadvantages compared with a theoretical approach. We did not develop specific generalized formulae to compare the topologies. However, do not be mistaken in believing that we reached the above conclusions based on a particular example. Similar results were obtained for power supplies ranging in power from 500W to 10kW, and output voltages of 3.3V, 5V, 12V, 24/27V, 48/54V.
  • In one article I found the following statement: "... the current doubler output stage needs twice the number of turns on the secondary side 'then its full wave counter part, but only one winding is needed ...". Let's not play with words. A current doubler power transformer has the SAME total number of turns on the secondary as its center tap equivalent.
  • Core loss, in the output inductors incorrectly scaled to twice the value for the center tap, is much higher, and may require only ferrite material to be used.
  • If you correctly design the current doubler topology to preserve the same currents in the primary side, you end up with a much higher output inductor compared with the center tap. However, the required output capacitance for the same output voltage ripple will be significantly lower. The result is that the total energy stored in the output stage is significantly lower, because, usually, most of the energy is stored in output capacitors and not in the output inductor(s).
  • The voltage loop of the output stage is different in center tap then in current double, and the compensation network has to be changed.
  • For the current doubler topology to work properly, the currents in the two output inductors have to be balanced. In order to have them balanced, you can not use voltage mode control or average current mode control for the output stage. You MUST use peak current mode control or a similar control method to force equal average currents in the two output inductors.
  • Some of the current doubler advantages: lower loss in the power transformer, simpler mechanical structure for the output transformer, and lower output capacitance required for the same voltage ripple.
  • When the current doubler should be consider as an alternative to center tap: output currents over 100A for fan cooled, and over 25A for natural convection cooled. For currents below 100A in fan cooled units or below 25A for natural convection cooled units, we consider that the center tap topology is still a better alternative.
  • Do not rush to conclusions such as which topology is better after just reading technical articles. Use your own judgment for your particular application, considering: maintaining same currents in the primary side, calculating ALL losses in ALL the magnetics components, calculating ALL costs (parts and labor), etc.

Note: For information regarding formula and Spice simulation files used in the article click on: SMPS Design spreadsheet and SMPS PSpice Simulation .

Current Doubler topology, prior art:
  • 1930 - 1940 ? Topology used with vacuum tubes.
  • 1987 July 22, Denmark patent DK1987000003826, Ole S. Seiersen.
  • 1988 July 21, US patent filed, Ole S. Seiersen.
  • 1990 Feb 6, US patent 4,899,271, Ole S. Seiersen.
  • 1991 Jun, HFPC Proceedings, "A New Efficient High Frequency Rectifier Circuit" by C. Peng, M. Hannigan and O. Seiersen. Topology name: "Hybridge".
  • 1991 Jun, HFPC Proceedings, "A New Output Rectifier Configuration Optimized For High Frequency Operation" by Kevan O'Meara. The topology is not explicitly named "Current Doubler topology", but it is emphasized the "... output current doubling property ...".
  • 1994 Dec, Unitrode Design Note DN-63, "The Current-Doubler Rectifier: An Alternative Rectification Technique For Push-Pull And Bridge Converters", by Laszlo Balogh.
SMPS Intellectual Property
This article contains information for which SMPS Power Supplies and its partners may claim Copyright and/or Trademark rights and may be subject of a Patent application. Also SMPS Power Supplies and its partners may claim the status of "First to be published", relative to ideas published in this article. Reasonable parts of this article may be quoted by any third parties, without contacting us, assuming that the source is clearly identified and a link to the full article is included. If you wish to incorporate information from this article within a commercial product, you should contact us for permission.
  • First Revision: 14 Feb 1998
  • Web first published: 17 Feb 2000
  • Last Revision: 28 Aug 2002

Protected by:

Copyright © SMPS Power Supplies ™. All rights reserved.